Computer Architecture
Complete CA Exam Guide

✔ Model Answer

Definitions:

• Bit: The smallest unit of information in a computer, capable of storing a binary value of 0 or 1. [1 mark]
• Byte: A group of 8 bits that can be treated as an atomic unit. It is the standard unit for expressing memory size. [1 mark]
• Word: The smallest addressable entity in memory, consisting of n bits that can be stored or retrieved in a single memory operation. Typical sizes range from 16 to 64 bits. [1 mark]

Address bits for 512 MB:

512 MB = 512 × 2²⁰ = 2⁹ × 2²⁰ = 2²⁹ bytes

Maximum capacity with 32-bit address bus:

✔ Model Answer

A memory write operation stores a word from the CPU into a specified memory location. The two key registers involved are the Memory Data Register (MDR) and the Memory Address Register (MAR).

Three Steps of a Memory Write:

1. Load MDR: The word to be written is loaded by the CPU into the Memory Data Register (MDR). The MDR acts as a temporary buffer holding the data to be stored. [2 marks]
2. Load MAR: The address of the memory location where the word is to be stored is loaded into the Memory Address Register (MAR). The MAR holds the destination address. [2 marks]
3. Issue WRITE Signal: The CPU issues a WRITE control signal. This triggers the memory system to store the word currently in the MDR into the memory location whose address is held in the MAR. [2 marks]

Register Roles (Table):

✔ Model Answer

Three Steps of a Memory Read:

1. Load MAR: The address of the memory location from which the word is to be read is loaded into the MAR. [1 mark]
2. Issue READ Signal: The CPU issues a READ control signal, indicating that the word at the address held in MAR should be transferred into the MDR. [1 mark]
3. Data Available in MDR: After a period equal to the memory access delay, the memory system places the requested word into the MDR, where it is ready for CPU processing. [2 marks]

Key Difference between READ and WRITE:

✔ Model Answer

Why "One-and-half" Address?

The instruction uses a memory location (full address bits needed) AND a register (fewer bits needed). Since the memory operand requires a full address while the register needs only a small field, the combined addressing requirement is described as "one-and-a-half" addresses.

Stack Operation (Zero-address) — Push & Pop:

• PUSH: Store a value at address pointed to by Stack Pointer (SP), then increment SP.
• POP: Decrement SP first, then retrieve the value at that address. LIFO — last in, first out.

✔ Model Answer

Addressing mode: The method by which the address of an operand is specified in an instruction. Different modes offer trade-offs between instruction size, flexibility, and speed.

Key Comparison — Indirect vs. Indexed:

• Indirect: One extra memory access to get the address. Flexible for dynamic pointer-like access.
• Indexed: Uses arithmetic (addition) to compute the address. Ideal for array traversal — increment X to access successive elements.

✔ Model Answer

✔ Model Answer

Advantage of Memory Indirect:

Allows access to a larger address space — the pointer can be stored anywhere in memory, unlike register indirect which is limited by the number of registers available.

Disadvantage of Memory Indirect:

Requires an extra memory read cycle to fetch the effective address, making it significantly slower than register indirect addressing.

✔ Model Answer

1. Data Movement Instructions [3 marks]

Transfer data between registers, between registers and memory, or to/from the stack. They do NOT modify the data.

• MOV Ri, Rj — Copies content of Ri into Rj. Rj is overwritten; Ri unchanged.
• LOAD 25838, Rj — Loads content of memory address 25838 into register Rj. Memory unchanged.
• STORE Ri, 1024 — Stores content of Ri into memory location 1024. Ri unchanged.

2. Arithmetic & Logical Instructions [3 marks]

Perform computation or logical manipulation on register/memory contents.

• ADD R1,R2,R0 — R0 ← R1 + R2. Source registers unchanged.
• SHIFT R1 — Performs logical left or right shift on R1.
• AND R1,R2 — Bitwise AND of R1 and R2, stored in R2.

3. Sequencing / Control Instructions [3 marks]

Change the order of instruction execution by modifying the Program Counter (PC).

• JUMP NEW-ADDRESS — Unconditional: PC ← NEW-ADDRESS. Previous PC value is lost.
• BRANCH-IF-ZERO Loop — Conditional: if Z flag = 1, PC ← Loop address.
• CALL SubroutineX — Pushes return address, PC ← SubroutineX.

4. Input/Output Instructions [3 marks]

Transfer data between the processor and external peripheral devices through dedicated ports.

• INPUT 1000 — Reads data from the input device at port address 1000 into the accumulator.
• OUTPUT 2000 — Sends data from the accumulator to the output device at port address 2000.

✔ Model Answer

The Condition Code (CC) Register is a special-purpose register whose individual bits (flags) are set or cleared based on the results of executing various instructions. It is used by conditional branch instructions to decide whether to take a branch.

Example: Assembly Loop Using Conditional Branching

The DECREMENT instruction updates the Z flag. If R1 is not yet zero (Z=0, meaning result > 0), the branch is taken and the loop continues. When R1 reaches 0, Z=1, the branch is NOT taken, and execution falls through.

✔ Model Answer

Why RETURN is needed after CALL:

When CALL executes, the incremented PC value (pointing to the instruction AFTER the CALL) is pushed onto the stack. The RETURN instruction pops this saved address from the stack back into the PC, thereby resuming execution exactly where the program left off before the subroutine was called.

Without RETURN, execution would continue inside the subroutine indefinitely or fall into incorrect memory. CALL + RETURN together implement the function call mechanism.

✔ Model Answer

Dedicated I/O: The CPU uses special I/O instructions (INPUT, OUTPUT) with dedicated port addresses that are separate from the memory address space.

Memory-mapped I/O: I/O device registers are mapped into the same address space as regular memory. The CPU interacts with I/O devices using standard data movement instructions (MOVE, LOAD, STORE) — no separate INPUT/OUTPUT instructions needed.

Advantage of memory-mapped I/O: Any instruction that can reference memory can be used to access I/O devices, giving the programmer the full power of the instruction set for I/O operations without needing special I/O instructions.

✔ Model Answer

✔ Model Answer

(a) Addition — Two numbers from memory [5 marks]

(b) Subtraction — 9 minus 4 [5 marks]

✔ Model Answer

How CMP works internally:

CMP performs a subtraction (AL − BL) but does NOT store the result. It ONLY updates the Condition Code flags (N, Z, V, C) based on the outcome. These flags are then examined by a subsequent conditional jump instruction.

✔ Model Answer

Assembly language is a low-level programming language that uses mnemonic instructions (e.g., MOV, ADD, SUB) that map directly to machine code instructions. An assembler translates assembly code into binary machine code.

Advantages [3 marks]:

1. Efficiency: Programs run faster and use less memory since the programmer has direct control over hardware resources with no abstraction overhead.
2. Direct hardware control: Allows precise manipulation of registers, memory addresses, and I/O ports — essential for OS kernels, device drivers, and embedded systems.
3. Size optimisation: Code can be tuned for minimal footprint, critical in microcontrollers and ROM-based systems.

Disadvantages [2 marks]:

1. Low portability: Code written for one CPU architecture (e.g., x86) must be completely rewritten for another (e.g., ARM).
2. Harder to maintain: Programs are longer, more complex, and harder to read/debug compared to equivalent high-level language code.

Common Use Cases:

Operating systems, embedded systems, device drivers, microcontrollers, and game engines (performance-critical sections).

✔ Model Answer

(a) Number of addressable words:

(b) Total capacity in bytes:

(c) Capacity in MB:

✔ Model Answer

(a) Instruction class: One-and-half-address instruction. [2 marks]
It is called "one-and-half" because it uses a memory operand (B — requires full address bits) and a register operand (R1 — requires fewer bits for a register field).

(b) Addressing modes: [2 marks]

• Operand B: Direct (Absolute) addressing — B is the address of a memory location.
• Operand R1: Register addressing — R1 is a CPU register.

(c) Equivalent three-address instruction: [2 marks]

(d) Effect on operands: [2 marks]

• Contents of memory location B: UNCHANGED — B is only read, not written to.
• Contents of register R1: OVERWRITTEN — R1 receives the result (M[B] + R1). The original value of R1 is lost.

✔ Model Answer

Strategy: The simple processor uses AC as accumulator and DR as data register. ADD always does: AC ← AC + DR.

The result A+B+C is stored in memory location "Result". This demonstrates why one-address (accumulator-based) architectures require more instructions than three-address architectures for the same computation.

✔ Model Answer

A stack is a LIFO (Last-In, First-Out) data structure. The Stack Pointer (SP) always points to the top of the stack — the next usable location.

PUSH Operation (storing value 5A):

POP Operation (retrieving value DD from 1021):

✔ Model Answer

CISC — Complex Instruction Set Computer:

CISC architectures support many instruction classes (including one-and-half and three-address forms) and rich addressing modes (including memory indirect). A single instruction can perform multiple memory accesses. This reduces the number of instructions per program but each instruction may take multiple clock cycles.

RISC — Reduced Instruction Set Computer:

RISC architectures limit instructions to simple, single-cycle operations. Only LOAD and STORE access memory; all arithmetic uses register operands only (three-address register-to-register). Addressing modes are minimal (typically immediate and register indirect only).

Relevance to Course Material:

The course material covers a range of addressing modes and instruction classes consistent with a CISC-like instructional model (especially memory indirect, indexed, and one-and-half address formats). However, the simple processor mnemonics (LD, ST, ADD) and the emphasis on the accumulator model lean toward an early RISC/simple processor philosophy. Understanding both is essential because modern CPUs blend both approaches.